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With technology scaling, the size of cache systems in chip-multiprocessors(CMPs) has been dramatically increased to efficiently store and manipulate alarge amount of data in future applications and decrease the gap between coresand off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCshas been recently introduced as a new methodology to combat to performancechallenges of 2D integration and the memory wall. However, the 3D design ofSRAM LLCs has made the thermal problem even more severe. It, therefore, incursmore leakage energy consumption than conventional SRAM cache architectures in2Ds due to dense integration. In this paper, we propose two differentarchitectures that exploit the data compression to reduce the energy of LLC andinterconnects in 3D-ICs.

Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression