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Recent years have witnessed an unprecedented surge of interest, from socialnetworks to drug discovery, in learning representations of graph-structureddata. However, graph neural networks, the machine learning models for handlinggraph-structured data, face significant challenges when running on conventionaldigital hardware, including von Neumann bottleneck incurred by physicallyseparated memory and processing units, slowdown of Moore's law due totransistor scaling limit, and expensive training cost. Here we present a novelhardware-software co-design, the random resistor array-based echo state graphneural network, which addresses these challenges. The random resistor arraysnot only harness low-cost, nanoscale and stackable resistors for highlyefficient in-memory computing using simple physical laws, but also leverage theintrinsic stochasticity of dielectric breakdown to implement random projectionsin hardware for an echo state network that effectively minimizes the trainingcost thanks to its fixed and random weights. The system demonstratesstate-of-the-art performance on both graph classification using the MUTAG andCOLLAB datasets and node classification using the CORA dataset, achieving34.2x, 93.2x, and 570.4x improvement of energy efficiency and 98.27%, 99.46%,and 95.12% reduction of training cost compared to conventional graph learningon digital hardware, respectively, which may pave the way for the nextgeneration AI system for graph learning.

Echo state graph neural networks with analogue random resistor arrays