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The advent of switches with programmable dataplanes has enabled the rapiddevelopment of new network functionality, as well as providing a platform foracceleration of a broad range of application-level functionality. However,existing switch hardware was not designed with application acceleration inmind, and thus applications requiring operations or datatypes not used intraditional network protocols must resort to expensive workarounds.Applications involving floating point data, including distributed training formachine learning and distributed query processing, are key examples.  In this paper, we propose FPISA, a floating point representation designed towork efficiently in programmable switches. We first implement FPISA on an IntelTofino switch, but find that it has limitations that impact throughput andaccuracy. We then propose hardware changes to address these limitations basedon the open-source Banzai switch architecture, and synthesize them in a 15-nmstandard-cell library to demonstrate their feasibility. Finally, we use FPISAto implement accelerators for training for machine learning and for queryprocessing, and evaluate their performance on a switch implementing our changesusing emulation. We find that FPISA allows distributed training to use 25-75%fewer CPU cores and provide up to 85.9% better throughput in a CPU-constrainedenvironment than SwitchML. For distributed query processing with floating pointdata, FPISA enables up to 2.7x better throughput than Spark.

Unlocking the Power of Inline Floating-Point Operations on Programmable Switches