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Systolic arrays have been widely used for accelerating HPC and deep learningapplications. There is a plethora of previous works on the performance tuningof systolic arrays, but usually based on a number of oversimplified assumptions(e.g., only considering divisors for loop tiling, pruning based on off-chipdata communication) to reduce the design space.  In this paper, we present a comprehensive design space exploration tool namedOdyssey for systolic array optimization. Odyssey does not rely on artificialassumptions to limit the design space, and yet it is highly efficient andscalable with a hybrid optimization technique. For example, for a1024x1024x1024 matrix multiplication, it finds designs that reach 90% of theoptimal performance in 5 seconds with a single CPU thread. Moreover, usingOdyssey, we unveil and quantify the suboptimality introduced by multiplecommonly used oversimplifications in prior studies for systolic array designspace exploration. For example, Odyssey results show that limiting to divisorsfor loop tiling leads to a 39% performance loss, and pruning based on off-chipdata movement results in a 45% performance loss. We applied Odyssey to explorethe architecture trade-offs for matrix multiplication and convolutional neuralnetwork, providing inspiration into possible optimizations for these twoapplications.

Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned