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As spiking-based deep learning inference applications are increasing inembedded systems, these systems tend to integrate neuromorphic acceleratorssuch as $\mu$Brain to improve energy efficiency. We propose a $\mu$Brain-basedscalable many-core neuromorphic hardware design to accelerate the computationsof spiking deep convolutional neural networks (SDCNNs). To increase energyefficiency, cores are designed to be heterogeneous in terms of their neuron andsynapse capacity (big cores have higher capacity than the little ones), andthey are interconnected using a parallel segmented bus interconnect, whichleads to lower latency and energy compared to a traditional mesh-basedNetwork-on-Chip (NoC). We propose a system software framework called SentryOSto map SDCNN inference applications to the proposed design. SentryOS consistsof a compiler and a run-time manager. The compiler compiles an SDCNNapplication into subnetworks by exploiting the internal architecture of big andlittle $\mu$Brain cores. The run-time manager schedules these sub-networks ontocores and pipeline their execution to improve throughput. We evaluate theproposed big little many-core neuromorphic design and the system softwareframework with five commonlyused SDCNN inference applications and show that theproposed solution reduces energy (between 37% and 98%), reduces latency(between 9% and 25%), and increases application throughput (between 20% and36%). We also show that SentryOS can be easily extended for other spikingneuromorphic accelerators.

Design of Many-Core Big Little \mu Brain for Energy-Efficient Embedded Neuromorphic Computing