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Engineering is an important domain for supercomputing, with the Alya modelbeing a popular code for undertaking such simulations. With ever increasingdemand from users to model larger, more complex systems at reduced time tosolution it is important to explore the role that novel hardware technologies,such as FPGAs, can play in accelerating these workloads on future exascalesystems.  In this paper we explore the porting of Alya's incompressible flow matrixassembly kernel, which accounts for a large proportion of the model runtime,onto FPGAs. After describing in detail successful strategies for optimisationat the kernel level, we then explore sharing the workload between the FPGA andhost CPU, mapping most appropriate parts of the kernel between thesetechnologies, enabling us to more effectively exploit the FPGA. We then comparethe performance of our approach on a Xilinx Alveo U280 against a 24-core XeonPlatinum CPU and Nvidia V100 GPU, with the FPGA significantly out-performingthe CPU and performing comparably against the GPU, whilst drawing substantiallyless power. The result of this work is both an experience report describingappropriate dataflow optimisations which we believe can be applied more widelyas a case-study across HPC codes, and a performance comparison for thisspecific workload that demonstrates the potential for FPGAs in accelerating HPCengineering simulations.

Porting incompressible flow matrix assembly to FPGAs for accelerating HPC engineering simulations