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Semiconductor design houses rely on third-party foundries to manufacturetheir integrated circuits (IC). While this trend allows them to tacklefabrication costs, it introduces security concerns as external (and potentiallymalicious) parties can access critical parts of the designs and steal or modifythe Intellectual Property (IP). Embedded FPGA (eFPGA) redaction is a promisingtechnique to protect critical IPs of an ASIC by \textit{redacting} (i.e.,removing) critical parts and mapping them onto a custom reconfigurable fabric.Only trusted parties will receive the correct bitstream to restore the redactedfunctionality. While previous studies imply that using an eFPGA is a sufficientcondition to provide security against IP threats like reverse-engineering,whether this truly holds for all eFPGA architectures is unclear, thusmotivating the study in this paper. We examine the security of eFPGA fabricsgenerated by varying different FPGA design parameters. We characterize thepower, performance, and area (PPA) characteristics and evaluate each fabric'sresistance to SAT-based bitstream recovery. Our results encourage designers towork with custom eFPGA fabrics rather than off-the-shelf commercial FPGAs andreveals that only considering a redaction fabric's bitstream size is inadequatefor gauging security.

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction