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Due to the globalization of Integrated Circuit (IC) supply chain, hardwaretrojans and the attacks that can trigger them have become an important securityissue. One type of hardware Trojans leverages the don't care transitions inFinite State Machines (FSMs) of hardware designs. In this paper, we present asymbolic approach to detecting don't care transitions and the hidden Trojans.Our detection approach works at both RTL and gate-level, does not require agolden design, and works in three stages. In the first stage, it explores thereachable states. In the second stage, it performs an approximate analysis tofind the don't care transitions. In the third stage, it performs a state-spaceexploration from reachable states that have incoming don't care transitions tofind behavioral discrepancies with respect to what has been observed in thefirst stage. We also present a pruning technique based on the reachability ofFSM states. We present a methodology that leverages both RTL and gate-level forsoundness and efficiency. Specifically, we show that don't care transitionsmust be detected at the gate-level, i.e., after synthesis has been performed,for soundness. However, under specific conditions, Trojan detection can beperformed more efficiently at RTL. Evaluation of our approach on a set ofbenchmarks from OpenCores and TrustHub and using gate-level representationgenerated by two synthesis tools, Yosys and Synopsis Design Compiler (SDC),shows that our approach is both efficient (up to 10X speedup w.r.t. no pruning)and precise (0% false positives) in detecting don't care transitions and theTrojans that leverage them. Additionally, the total analysis time can achieveup to 3.40X (using Yosys) and 2.52X (SDC) speedup when synthesis preserves theFSM structure and the Trojan detection is performed at RTL.

A Symbolic Approach to Detecting Hardware Trojans Triggered by Don't Care Transitions