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Modern x86 processors have many prefetch instructions that can be used byprogrammers to boost performance. However, these instructions may also causesecurity problems. In particular, we found that on Intel processors, there aretwo security flaws in the implementation of PREFETCHW, an instruction foraccelerating future writes. First, this instruction can execute on data withread-only permission. Second, the execution time of this instruction leaks thecurrent coherence state of the target data.  Based on these two design issues, we build two cross-core private cacheattacks that work with both inclusive and non-inclusive LLCs, namedPrefetch+Reload and Prefetch+Prefetch. We demonstrate the significance of ourattacks in different scenarios. First, in the covert channel case,Prefetch+Reload and Prefetch+Prefetch achieve 782 KB/s and 822 KB/s channelcapacities, when using only one shared cache line between the sender andreceiver, the largest-to-date single-line capacities for CPU cache covertchannels. Further, in the side channel case, our attacks can monitor the accesspattern of the victim on the same processor, with almost zero error rate. Weshow that they can be used to leak private information of real-worldapplications such as cryptographic keys. Finally, our attacks can be used intransient execution attacks in order to leak more secrets within the transientwindow than prior work. From the experimental results, our attacks allowleaking about 2 times as many secret bytes, compared to Flush+Reload, which iswidely used in transient execution attacks.

Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks