English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

In this paper, we consider the HLS implementation of a three-dimensionalsystolic array architecture for matrix multiplication that targets specificcharacteristics of Intel Stratix 10 FPGAs in order to produce designs thatachieve a high floating-point throughput using most of the DSPs at highfrequencies in a way that avoids the congestion of the routing fabric. Theinvestigated three-dimensional systolic array architecture is able to producehardware designs that use 99% of the available DSPs with maximum frequenciesthat let us achieve performances above 3 TFLOPS.

High Level Synthesis Implementation of a Three-dimensional Systolic Array Architecture for Matrix Multiplications on Intel Stratix 10 FPGAs