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Reverse engineering (RE) in Integrated Circuits (IC) is a process in whichone will attempt to extract the internals of an IC, extract the circuitstructure, and determine the gate-level information of an IC. In general, REprocess can be done for validation as well as intellectual property (IP)stealing intentions. In addition, RE also facilitates different illicitactivities such as insertion of hardware Trojan, pirate, or counterfeit adesign, or develop an attack. In this work, we propose an approach to introducecognitive perturbations, with the aid of adversarial machine learning, to theIC layout that could prevent the RE process from succeeding. We first constructa layer-by-layer image dataset of 45nm predictive technology. With thisdataset, we propose a conventional neural network model called RecoG-Net torecognize the logic gates, which is the first step in RE. RecoG-Net issuccessfully to recognize the gates with more than 99.7% accuracy. Ourthwarting approach utilizes the concept of the adversarial attack generationalgorithms to generate perturbation. Unlike traditional adversarial attacks inmachine learning, the perturbation generation needs to be highly constrained tomeet the fab rules such as Design Rule Checking (DRC) Layout vs. Schematic(LVS) checks. Hence, we propose CAPTIVE as an constrained perturbationgeneration satisfying the DRC. The experiments shows that the accuracy ofreverse engineering using machine learning techniques can decrease from 100% toapproximately 30% based on the adversary generator.

CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering