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On-chip memory (usually based on Static RAMs-SRAMs) are crucial componentsfor various computing devices including heterogeneous devices, e.g., GPUs,FPGAs, ASICs to achieve high performance. Modern workloads such as Deep NeuralNetworks (DNNs) running on these heterogeneous fabrics are highly dependent onthe on-chip memory architecture for efficient acceleration. Hence, improvingthe energy-efficiency of such memories directly leads to an efficient system.One of the common methods to save energy is undervolting i.e., supply voltageunderscaling below the nominal level. Such systems can be safely undervoltedwithout incurring faults down to a certain voltage limit. This safe range isalso called voltage guardband. However, reducing voltage below the guardbandlevel without decreasing frequency causes timing-based faults.  In this paper, we propose MoRS, a framework that generates the firstapproximate undervolting fault model using real faults extracted fromexperimental undervolting studies on SRAMs to build the model. We inject thefaults generated by MoRS into the on-chip memory of the DNN accelerator toevaluate the resilience of the system under the test. MoRS has the advantage ofsimplicity without any need for high-time overhead experiments while beingaccurate enough in comparison to a fully randomly-generated fault injectionapproach. We evaluate our experiment in popular DNN workloads by mappingweights to SRAMs and measure the accuracy difference between the output of theMoRS and the real data. Our results show that the maximum difference betweenreal fault data and the output fault model of MoRS is 6.21%, whereas themaximum difference between real data and random fault injection model is 23.2%.In terms of average proximity to the real data, the output of MoRS outperformsthe random fault injection approach by 3.21x.

MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs