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In-memory computing (IMC) is an effectual solution for energy-efficientartificial intelligence applications. Analog IMC amortizes the powerconsumption of multiple sensing amplifiers with analog-to-digital converter(ADC), and simultaneously completes the calculation of multi-line data withhigh parallelism degree. Based on a universal one-transistor one-magnetictunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, thispaper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifyingmethod to realize analog IMC. Previous concerns include low TMR ratio andanalog calculation nonlinearity are addressed using device-circuit interaction.Peripheral circuits are minimally modified to enable in-memory matrix-vectormultiplication. A current mirror with feedback structure is implemented toenhance analog computing linearity and calculation accuracy. The proposeddesign maximumly supports 1024 2-bit input and 1-bit weightmultiply-and-accumulate (MAC) computations simultaneously. The 2-bit input isrepresented by the width of the input (IN) pulses, while the 1-bit weight isstored in STT-MRAM and the x7500 magnified TMR (m-TMR) ratio is obtained bylatching. The proposal is simulated using 28-nm CMOS process and MTJ compactmodel. The integral nonlinearity is reduced by 57.6% compared with theconventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bitweight and 4-bit output convolution neural network (CNN).

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell