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In this paper, we propose a 'full-stack' solution to designing high capacityand low latency on-chip cache hierarchies by starting at the circuit level ofthe hardware design stack. First, we propose a novel Gain Cell (GC) designusing FDSOI. The GC has several desirable characteristics, including ~50%higher storage density and ~50% lower dynamic energy as compared to thetraditional 6T SRAM, even after accounting for peripheral circuit overheads. Wealso exploit back-gate bias to increase retention time to 1.12 ms (~60x ofeDRAM) which, combined with optimizations like staggered refresh, makes it anideal candidate to architect all levels of on-chip caches. We show thatcompared to 6T SRAM, for a given area budget, GC based caches, on average,provide 29% and 36% increase in IPC for single- and multi-programmed workloads,respectively on contemporary workloads including SPEC CPU2017. We also observedynamic energy savings of 42% and 34% for single- and multi-programmedworkloads, respectively.  We utilize the inherent properties of the proposed GC, including decoupledread and write bitlines to devise optimizations to save precharge energy andarchitect GC caches with better energy and performance characteristics.Finally, in a quest to utilize the best of all worlds, we combine GC withSTT-RAM to create hybrid hierarchies. We show that a hybrid hierarchy with GCcaches at L1 and L2, and an LLC split between GC and STT-RAM, with asymmetricwrite optimization enabled, is able to provide a 54% benefit in energy-delayproduct (EDP) as compared to an all-SRAM design, and 13% as compared to anall-GC cache hierarchy, averaged across multi-programmed workloads.

HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy