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This dissertation rigorously characterizes many modern commodity DRAM devicesand shows that by exploiting DRAM access timing margins withinmanufacturer-recommended DRAM timing specifications, we can significantlyimprove system performance, reduce power consumption, and improve devicereliability and security. First, we characterize DRAM timing parameter marginsand find that certain regions of DRAM can be accessed faster than other regionsdue to DRAM cell process manufacturing variation. We exploit this by enablingvariable access times depending on the DRAM cells being accessed, which notonly improves overall system performance, but also decreases power consumption.Second, we find that we can uniquely identify DRAM devices by the locations offailures that result when we access DRAM with timing parameters reduced belowspecification values. Because we induce these failures with DRAM accesses, wecan generate these unique identifiers significantly more quickly than priorwork. Third, we propose a random number generator that is based on ourobservation that timing failures in certain DRAM cells are randomly induced andcan thus be repeatedly polled to very quickly generate true random values.Finally, we characterize the RowHammer security vulnerability on a wide rangeof modern DRAM chips while violating the DRAM refresh requirement in order todirectly characterize the underlying DRAM technology without the interferenceof refresh commands. We demonstrate with our characterization of real chips,that existing RowHammer mitigation mechanisms either are not scalable or sufferfrom prohibitively large performance overheads in projected future devices andit is critical to research more effective solutions to RowHammer. Overall, ourstudies build a new understanding of modern DRAM devices to improve computingsystem performance, reliability and security all at the same time.

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins