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In this paper, a method for learning a recurrent neural network (RNN)controller that maximizes the robustness of signal temporal logic (STL)specifications is presented. In contrast to previous methods, we considersynthesizing the RNN controller for which the user is able to select an STLspecification arbitrarily from multiple STL specifications. To obtain such acontroller, we propose a novel notion called STL2vec, which represents a vectorrepresentation of the STL specifications and exhibits their similarities. Theconstruction of the STL2vec is useful since it allows us to enhance theefficiency and performance of the RNN controller. We validate our proposedmethod through the examples of the path planning problem.

STL2vec: Signal Temporal Logic Embeddings for Control Synthesis With Recurrent Neural Networks