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This report presents some early results on code generation targeting tensorcores on NVIDIA GPUs using the MLIR compiler infrastructure. Thestate-of-the-art in high-performance deep learning today is primarily driven bymanually optimized highly tuned libraries. The approach to develop suchlibraries is often not modular or reusable to the same extent that compilerinfrastructure like LLVM is. Manual optimization typically does not use astandard intermediate representation (IR), although the optimizations performedcan be encoded as a sequence of transformation steps and customized passes onan IR. Hand tuning may also miss exploration of design points only reachableeasily by automatic code generation. We believe that until the recentintroduction of MLIR (Multi-level intermediate representation), IRinfrastructure was not geared to tackle the problem of automatic generation ofdomain-specific libraries in an effective manner. In particular, it was hard torepresent and transform compute abstractions at high, middle, and low levelsusing a single IR.  With suitable abstractions in MLIR, we build an experimental loweringpipeline that is able to automatically generate code for matrix-matrixmultiplication on NVIDIA GPUs targeting its tensor cores. On a set of problemsizes we evaluated, initial performance results show that we are able to attainperformance that is 95-119% and 80-160% of CuBLAS for FP32 and FP16 accumulaterespectively on NVIDIA's Ampere microarchitecture-based Geforce 3090 RTX. Webelieve that these results could be used as motivation for further research anddevelopment on automatic code and library generation using IR infrastructurefor similar specialized accelerators.

High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results