English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

The design of many-core neuromorphic hardware is getting more and morecomplex as these systems are expected to execute large machine learning models.To deal with the design complexity, a predictable design flow is needed toguarantee real-time performance such as latency and throughput withoutsignificantly increasing the buffer requirement of computing cores. SynchronousData Flow Graphs (SDFGs) are used for predictable mapping of streamingapplications to multiprocessor systems. We propose an SDFG-based design flowfor mapping spiking neural networks (SNNs) to many-core neuromorphic hardwarewith the objective of exploring the tradeoff between throughput and buffersize. The proposed design flow integrates an iterative partitioning approach,based on Kernighan-Lin graph partitioning heuristic, creating SNN clusters suchthat each cluster can be mapped to a core of the hardware. The partitioningapproach minimizes the inter-cluster spike communication, which improveslatency on the shared interconnect of the hardware. Next, the design flow mapsclusters to cores using an instance of the Particle Swarm Optimization (PSO),an evolutionary algorithm, exploring the design space of throughput and buffersize. Pareto optimal mappings are retained from the design flow, allowingsystem designers to select a Pareto mapping that satisfies throughput andbuffer size requirements of the design. We evaluated the design flow using fivelarge-scale convolutional neural network (CNN) models. Results demonstrate 63%higher maximum throughput and 10% lower buffer size requirement compared tostate-of-the-art dataflow-based mapping solutions.

A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic Hardware