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Synchoros VLSI design style has been proposed as an alternative to thestandard cell best design style; the word synchoros is derived from the Greekword choros for space. Synchoricity discretises space with a virtual grid, theway synchronicity discretises time with clock ticks. SiLago (Silicon Lego)blocks are atomic synchoros building blocks like Lego bricks. SiLago blocksabsorb all metal layer details, i.e., all wires, to enable composition byabutment of valid; valid in the sense of being technology design rulescompliant, timing clean and OCV ruggedized. Effectively, composition byabutment eliminates logic and physical synthesis for the end user. Like Legosystem, synchoricity does need a finite number of SiLago block types to caterto different types of designs. Global NoCs are important system level designcomponents. In this paper, we show, how with a small library of SiLago blocksfor global NoCs, it is possible to automatically synthesize arbitrary globalNoCs of different types, dimensions, and topology. The synthesized global NoCsare not only valid VLSI designs, their cost metrics (area, latency, and energy)are known with post-layout accuracy in linear time. We argue that this isessential to be able to do chip-level design space exploration. We show how theabstract timing model of such global NoC SiLago blocks can be built and used toanalyse the timing of global NoC links with post layout accuracy and in lineartime. We validate this claim by subjecting the same VLSI designs of global NoCto commercial EDA's static timing analysis and show that the abstract timinganalysis enabled by synchoros VLSI design gives same results as the commercialEDA tools.

Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design