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Large-scale graph processing has drawn great attention in recent years. Mostof the modern-day datacenter workloads can be represented in the form of GraphProcessing such as MapReduce etc. Consequently, a lot of designs forDomain-Specific Accelerators have been proposed for Graph Processing. SpatialArchitectures have been promising in the execution of Graph Processing, wherethe graph is partitioned into several nodes and each node works in parallel. Weconduct experiments to analyze the on-chip movement of data in graph processingon a Spatial Architecture. Based on the observations, we identify a datamovement bottleneck, in the execution of such highly parallel processingaccelerators. To mitigate the bottleneck we propose a novel power-law awareGraph Partitioning and Data Mapping scheme to reduce the communication latencyby minimizing the hop counts on a scalable network-on-chip. The experimentalresults on popular graph algorithms show that our implementation makes theexecution 2-5x faster and 2.7-4x energy-efficient by reducing the data movementtime in comparison to a baseline implementation.

Efficient On-Chip Communication for Parallel Graph-Analytics on Spatial Architectures