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Tiled spatial architectures have proved to be an effective solution to buildlarge-scale DNN accelerators. In particular, interconnections between tiles arecritical for high performance in these tile-based architectures. In this work,we identify the inefficiency of the widely used traditional on-chip networksand the opportunity of software-hardware co-design. We propose METRO with thebasic idea of decoupling the traffic scheduling policies from hardware fabricsand moving them to the software level. METRO contains two modules working insynergy: METRO software scheduling framework to coordinate the traffics andMETRO hardware facilities to deliver the data based on software configurations.We evaluate the co-design using different flit sizes for synthetic study,illustrating its effectiveness under various hardware resource constraints, inaddition to a wide range of DNN models selected from real-world workloads. Theresults show that METRO achieves 56.3% communication speedup on average and upto 73.6% overall processing time reduction compared with traditional on-chipnetwork designs.

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators