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The level crossing analog-to-digital converters are meant for the effectiveconversion of sparse signals by construction. In these converters, thebandwidth-power trade-off requires a re-design of the comparators which takes alot of time and effort to reach the application optimum point. Inspired bysynchronous converters that have a dynamic power component that can be tradedwith bandwidth with the change of a clock frequency, a technique to allow suchtrade-off in the level crossing converter was developed. The resulting levelcrossing ADC has an input signal dependent dynamic power which can reach up to42\% OFF time during the conversion of sine waves, achieving 45.5% powerreduction in the simulated design with TSMC 180nm PDK.

A technique to enable frequency dependent power savings in a level crossing analog-to-digital converter