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The ubiquitous use of sensing and signal processing is increasingexponentially with the advance of the Internet of Everything (IoE). In thiscontext, the design of every time more power efficient sensor nodes is a must.Within these nodes, one of the most power-hungry components are theanalog-to-digital converters (ADC). These components are used everywhere totranslate real-world analog signals into computer intelligible digital signals.One of the promising architecture for the sensing of physiological signals isthe level crossing ADC due to the sparse characteristics of those signals. Oneof the challenges to improve the power efficiency of this type of ADC lies inthe use of continuous comparators to keep track of the input signal within thevoltage references. The aim of this work is to investigate the impact of usingcontinuous comparator which can be turned off without incurring error to theconversion of the level crossing ADC. New boundaries will be set for thecorrect behavior of the level crossing ADC together with the conditions forpower saving with the proposed architecture. A 1V 5-bits level crossing ADC wasimplemented using the TSMC 0.18um process and fabricated for laboratorymeasurements. The ADC consumes 12.2uW during tracking state and with theproposed technique, the reduction of the average power can go from 4.2% to45.5% depending on the activity and the type of the input signal.

A 1V 5-bits Low Power Level Crossing ADC with OFF state in idle time for bio-medical applications in 0.18um CMOS