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Quantitative finance is the use of mathematical models to analyse financialmarkets and securities. Typically requiring significant amounts of computation,an important question is the role that novel architectures can play inaccelerating these models in the future on HPC machines. In this paper weexplore the optimisation of an existing, open source, FPGA based Credit DefaultSwap (CDS) engine using High Level Synthesis (HLS). Developed by Xilinx, andpart of their open source Vitis libraries, the implementation of this enginecurrently favours flexibility and ease of integration over performance.  We explore redesigning the engine to fully embrace the dataflow approach,ultimately resulting in an engine which is around eight times faster on anAlveo U280 FPGA than the original Xilinx library version. We then compare fiveof our engines on the U280 against a 24-core Xeon Platinum Cascade Lake CPU,outperforming the CPU by around 1.55 times, with the FPGA consuming 4.7 timesless power and delivering around seven times the power efficiency of the CPU.

Optimisation of an FPGA Credit Default Swap engine by embracing dataflow techniques