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Digital single-flux quantum (SFQ) technology promises to meet the demands ofultra low power and high speed computing needed for future exascalesupercomputing platforms. However, clocking SFQ logic circuits remains achallenge due to the presence of a large number of on-chip clock sinks, andhence, decomposing large designs into multiple independent clock domainssimilar to CMOS, have been proposed. However, such clock domains demandefficient synchronizing First-in-first-out (FIFO) buffers and robust interfacesto safely transfer data from one clock domain to another. In this brief, wepropose such a FIFO synchronizer and clock-domain crossing interface for bothuni and bi-directional data transfer without any significant degradation of theclock frequency. Our proposal scales to complex gate-level pipelined SFQ logiccores while demonstrating extremely low Bit Error Rate (BER) and is unaffectedby noise, given current SFQ lithography feature sizes.

A High Performance and Robust FIFO Synchronizer-Interface for Crossing Clock Domains in SFQ Logic