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Modern hardware design trends have shifted towards specialized hardwareacceleration for computationally intensive tasks like machine learning andcomputer vision. While these complex workloads can be accelerated by commercialGPUs, domain-specific hardware is far more optimal when needing to meet thestringent memory, throughput, and power constraints of mobile and embeddeddevices. This paper proposes and evaluates a Binary-Enabled Architecture forNeural Network Acceleration (BEANNA), a neural network hardware acceleratorcapable of processing both floating point and binary network layers. Throughthe use of a novel 16x16 systolic array based matrix multiplier with processingelements that compute both floating point and binary multiply-adds, BEANNAseamlessly switches between high precision floating point and binary neuralnetwork layers. Running at a clock speed of 100MHz, BEANNA achieves a peakthroughput of 52.8 GigaOps/second when operating in high precision mode, and820 GigaOps/second when operating in binary mode. Evaluation of BEANNA wasperformed by comparing a hybrid network with floating point outer layers andbinary hidden layers to a network with only floating point layers. The hybridnetwork accelerated using BEANNA achieved a 194% throughput increase, a 68%memory usage decrease, and a 66% energy consumption decrease per inference, allthis at the cost of a mere 0.23% classification accuracy decrease on the MNISTdataset.

BEANNA: A Binary-Enabled Architecture for Neural Network Acceleration