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The combination of Winograd's algorithm and systolic array architecture hasdemonstrated the capability of improving DSP efficiency in acceleratingconvolutional neural networks (CNNs) on FPGA platforms. However, handlingarbitrary convolution kernel sizes in FPGA-based Winograd processing elementsand supporting efficient data access remain underexplored. In this work, we arethe first to propose an optimized Winograd processing element (WinoPE), whichcan naturally support multiple convolution kernel sizes with the same amount ofcomputing resources and maintains high runtime DSP efficiency. Using theproposed WinoPE, we construct a highly efficient systolic array accelerator,termed WinoCNN. We also propose a dedicated memory subsystem to optimize thedata access. Based on the accelerator architecture, we build accurate resourceand performance modeling to explore optimal accelerator configurations underdifferent resource constraints. We implement our proposed accelerator onmultiple FPGAs, which outperforms the state-of-the-art designs in terms of boththroughput and DSP efficiency. Our implementation achieves DSP efficiency up to1.33 GOPS/DSP and throughput up to 3.1 TOPS with the Xilinx ZCU102 FPGA. Theseare 29.1\% and 20.0\% better than the best solutions reported previously,respectively.

WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs