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The fine-grained relationship between form and function with respect to deepneural network architecture design and hardware-specific acceleration is onearea that is not well studied in the research literature, with form oftendictated by accuracy as opposed to hardware function. In this study, acomprehensive empirical exploration is conducted to investigate the impact ofdeep neural network architecture design on the degree of inference speedup thatcan be achieved via hardware-specific acceleration. More specifically, weempirically study the impact of a variety of commonly used macro-architecturedesign patterns across different architectural depths through the lens ofOpenVINO microprocessor-specific and GPU-specific acceleration. Experimentalresults showed that while leveraging hardware-specific acceleration achieved anaverage inference speed-up of 380%, the degree of inference speed-up varieddrastically depending on the macro-architecture design pattern, with thegreatest speedup achieved on the depthwise bottleneck convolution designpattern at 550%. Furthermore, we conduct an in-depth exploration of thecorrelation between FLOPs requirement, level 3 cache efficacy, and networklatency with increasing architectural depth and width. Finally, we analyze theinference time reductions using hardware-specific acceleration when compared tonative deep learning frameworks across a wide variety of hand-crafted deepconvolutional neural network architecture designs as well as ones found vianeural architecture search strategies. We found that the DARTS-derivedarchitecture to benefit from the greatest improvement from hardware-specificsoftware acceleration (1200%) while the depthwise bottleneck convolution-basedMobileNet-V2 to have the lowest overall inference time of around 2.4 ms.

Does Form Follow Function? An Empirical Exploration of the Impact of Deep Neural Network Architecture Design on Hardware-Specific Acceleration