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Euclids algorithm is widely used in calculating of GCD (Greatest CommonDivisor) of two positive numbers. There are various fields where this divisionis used such as channel coding, cryptography, and error correction codes. Thismakes the GCD a fundamental algorithm in number theory, so a number of methodshave been discovered to efficiently compute it. The main contribution of thispaper is to investigate a method that computes the GCD of two 32-bit numbersbased on Euclidean algorithm which targets six different Xilinx chips. Thecomplexity of this method that we call Optimized_GCDSAD is achieved byutilizing Sum of Absolute Difference (SAD) block which is based on a fastcarry-out generation function. The efficiency of the proposed architecture isevaluated based on criteria such as time (latency), area delay product (ADP)and space (slice number) complexity. The VHDL codes of these architectures havebeen implemented and synthesized through ISE 14.7. A detailed comparativeanalysis indicates that the proposed Optimized_GCDSAD method based on SAD blockoutperforms previously known results.

Area-Delay-Efficeint FPGA Design of 32-bit Euclid's GCD based on Sum of Absolute Difference