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Implementing embedded neural network processing at the edge requiresefficient hardware acceleration that couples high computational performancewith low power consumption. Driven by the rapid evolution of networkarchitectures and their algorithmic features, accelerator designs areconstantly updated and improved. To evaluate and compare hardware designchoices, designers can refer to a myriad of accelerator implementations in theliterature. Surveys provide an overview of these works but are often limited tosystem-level and benchmark-specific performance metrics, making it difficult toquantitatively compare the individual effect of each utilized optimizationtechnique. This complicates the evaluation of optimizations for new acceleratordesigns, slowing-down the research progress. This work provides a survey ofneural network accelerator optimization approaches that have been used inrecent works and reports their individual effects on edge processingperformance. It presents the list of optimizations and their quantitativeeffects as a construction kit, allowing to assess the design choices for eachbuilding block separately. Reported optimizations range from up to 10'000xmemory savings to 33x energy reductions, providing chip designers an overviewof design choices for implementing efficient low power neural networkaccelerators.

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs