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Neural networks have demonstrated their outstanding performance in a widerange of tasks. Specifically recurrent architectures based on long-short termmemory (LSTM) cells have manifested excellent capability to model timedependencies in real-world data. However, standard recurrent architecturescannot estimate their uncertainty which is essential for safety-criticalapplications such as in medicine. In contrast, Bayesian recurrent neuralnetworks (RNNs) are able to provide uncertainty estimation with improvedaccuracy. Nonetheless, Bayesian RNNs are computationally and memory demanding,which limits their practicality despite their advantages. To address thisissue, we propose an FPGA-based hardware design to accelerate BayesianLSTM-based RNNs. To further improve the overall algorithmic-hardwareperformance, a co-design framework is proposed to explore the most fittingalgorithmic-hardware configurations for Bayesian RNNs. We conduct extensiveexperiments on healthcare applications to demonstrate the improvement of ourdesign and the effectiveness of our framework. Compared with GPUimplementation, our FPGA-based design can achieve up to 10 times speedup withnearly 106 times higher energy efficiency. To the best of our knowledge, thisis the first work targeting acceleration of Bayesian RNNs on FPGAs.

Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator