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High-performance branch target buffers (BTBs) and the L1I cache are key tohigh-performance front-end. Modern branch predictors are highly accurate, butwith an increase in code footprint in modern-day server workloads, BTB and L1Imisses are still frequent. Recent industry trend shows usage of large BTBs(100s of KB per core) that provide performance closer to the ideal BTB alongwith a decoupled front-end that provides efficient fetch-directed L1Iinstruction prefetching. On the other hand, techniques proposed by academia,like BTB prefetching and using retire order stream for learning, fail toprovide significant performance with modern-day processor cores that are deeperand wider.  We solve the problem fundamentally by increasing the storage density of thelast-level BTB. We observe that not all branch instructions require a fullbranch target address. Instead, we can store the branch target as a branchoffset, relative to the branch instruction. Using branch offset enables the BTBto store multiple branches per entry. We reduce the BTB storage in half, but weobserve that it increases skewness in the BTB. We propose a skewed indexed andcompressed last-level BTB design called MicroBTB (MBTB) that stores multiplebranches per BTB entry. We evaluate MBTB on 100 industry-provided serverworkloads. A 4K-entry MBTB provides 17.61% performance improvement compared toan 8K-entry baseline BTB design with a storage savings of 47.5KB per core.

Micro BTB: A High Performance and Lightweight Last-Level Branch Target Buffer for Servers