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With the rapidly growing use of Convolutional Neural Networks (CNNs) inreal-world applications related to machine learning and Artificial Intelligence(AI), several hardware accelerator designs for CNN inference and training havebeen proposed recently. In this paper, we present ATRIA, a novel bit-pArallelsTochastic aRithmetic based In-DRAM Accelerator for energy-efficient andhigh-speed inference of CNNs. ATRIA employs light-weight modifications in DRAMcell arrays to implement bit-parallel stochastic arithmetic based accelerationof multiply-accumulate (MAC) operations inside DRAM. ATRIA significantlyimproves the latency, throughput, and efficiency of processing CNN inferencesby performing 16 MAC operations in only five consecutive memory operationcycles. We mapped the inference tasks of four benchmark CNNs on ATRIA tocompare its performance with five state-of-the-art in-DRAM CNN acceleratorsfrom prior work. The results of our analysis show that ATRIA exhibits only 3.5%drop in CNN inference accuracy and still achieves improvements of up to 3.2x inframes-per-second (FPS) and up to 10x in efficiency (FPS/W/mm2), compared tothe best-performing in-DRAM accelerator from prior work.

ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing