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Sparse Matrix Vector multiplication (SpMV) is one of basic building blocks inscientific computing, and acceleration of SpMV has been continuously required.In this research, we aim for accelerating SpMV on recent CPUs for sparsematrices that have a specific sparsity structure, namely a diagonallystructured sparsity pattern. We focus a hybrid storage format that combines theDIA and CSR formats, so-called the HDC format. First, we recall the importanceof introducing cache blocking techniques into HDC-based SpMV kernels. Next,based on the observation of the cache blocked kernel, we present a modifiedversion of the HDC formats, which we call the M-HDC format, in which partialdiagonal structures are expected to be more efficiently picked up. For theseSpMV kernels, we theoretically analyze the expected performance improvementbased on performance models. Then, we conduct comprehensive experiments onstate-of-the-art multi-core CPUs. By the experiments using typical matrices, weclarify the detailed performance characteristics of each SpMV kernel. We alsoevaluate the performance for matrices appearing in practical applications anddemonstrate that our approach can accelerate SpMV for some of them. Through thepresent paper, we demonstrate the effectiveness of exploiting partial diagonalstructures by the M-HDC format as a promising approach to accelerating SpMV onCPUs for a certain kind of practical sparse matrices.

Accelerating the SpMV kernel on standard CPUs by exploiting the partially diagonal structures