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Crossbar resistive memory with the 1 Selector 1 Resistor (1S1R) structure isattractive for nonvolatile, high-density, and low-latency storage-class memoryapplications. As technology scales down to the single-nm regime, the increasingresistivity of wordline/bitline becomes a limiting factor to devicereliability. This paper presents write/read communication channels whileconsidering the line resistance and device variabilities by statisticallyrelating the degraded write/read margins and the channel parameters. Binaryasymmetric channel (BAC) models are proposed for the write/read operations.Simulations based on these models suggest that the bit-error rate of devicesare highly non-uniform across the memory array. These models providequantitative tools for evaluating the trade-offs between memory reliability anddesign parameters, such as array size, technology nodes, and aspect ratio, andalso for designing coding-theoretic solutions that would be most effective forcrossbar memory. Method for optimizing the read threshold is proposed to reducethe raw bit-error rate (RBER). We propose two schemes for efficient channelcoding based on Bose-Chaudhuri-Hocquenghem (BCH) codes. An interleaved codingscheme is proposed to mitigate the non-uniformity of reliability and a locationdependent coding framework is proposed to leverage this non-uniformity. Both ofour proposed coding schemes effectively reduce the undetected bit-error rate(UBER).

Channel Models and Coding Solutions for 1S1R Crossbar Resistive Memory with High Line Resistance