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Automatic algorithm-hardware co-design for DNN has shown great success inimproving the performance of DNNs on FPGAs. However, this process remainschallenging due to the intractable search space of neural network architecturesand hardware accelerator implementation. Differing from existing hardware-awareneural architecture search (NAS) algorithms that rely solely on the expensivelearning-based approaches, our work incorporates integer programming into thesearch algorithm to prune the design space. Given a set of hardware resourceconstraints, our integer programming formulation directly outputs the optimalaccelerator configuration for mapping a DNN subgraph that minimizes latency. Weuse an accuracy predictor for different DNN subgraphs with differentquantization schemes and generate accuracy-latency pareto frontiers. With lowcomputational cost, our algorithm can generate quantized networks that achievestate-of-the-art accuracy and hardware performance on Xilinx Zynq (ZU3EG) FPGAfor image classification on ImageNet dataset. The solution searched by ouralgorithm achieves 72.5% top-1 accuracy on ImageNet at framerate 50, which is60% faster than MnasNet and 135% faster than FBNet with comparable accuracy.

HAO: Hardware-aware neural Architecture Optimization for Efficient Inference