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This paper introduces a versatile, multi-layered technology to help supportteaching and learning core computer architecture concepts. This technology,called CodeAPeel is already implemented in one particular form to describeinstruction processing in compiler, assembly, and machine layers of a genericinstruction set architecture by a comprehensive simulation of itsfetch-decode-execute cycle as well as animation of the behavior of its CPUregisters, RAM, VRAM, STACK memories, various control registers, and graphicsscreen. Unlike most educational CPU simulators that simulate a real processorsuch as MIPS or RISC-V, CodeAPeel is designed and implemented as a generic RISCinstruction set architecture simulator with both scalar and vector instructionsto provide a dual-mode processor simulator as described by Flynn'sclassification of SISD and SIMD processors. Vectorization of operations isbuilt into the instruction repertoire of CodeAPeel, making it straightforwardto simulate such processors with powerful vector instructions.

CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses