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Caches have been used to construct various types of covert and side channelsto leak information. Most existing cache channels exploit the timing differencebetween cache hits and cache misses. However, we introduce a new and broaderclassification of cache covert channel attacks: Hit+Miss, Hit+Hit, andMiss+Miss. We highlight that cache misses for cache lines in different statesmay have more significant time differences, and these can be used as timingchannels. Based on this classification, we propose a new stable and stealthyMiss+Miss cache channel. Write-back caches are widely deployed in modernprocessors. This paper presents in detail a way in which replacement latencydifferences can be used to construct timing-based channels (called WB channels)to leak information in a write-back cache. Any modification to a cache line bya sender will set it to the dirty state, and the receiver can observe thisthrough measuring the latency of replacing this cache set. We also demonstratehow senders could exploit a different number of dirty cache lines in a cacheset to improve transmission bandwidth with symbols encoding multiple bits. Thepeak transmission bandwidths of the WB channels in commercial systems can varybetween 1300 and 4400~kbps per cache set in a hyper-threaded setting withoutshared memory between the sender and the receiver. In contrast to most existingcache channels, which always target specific memory addresses, the new WBchannels focus on the cache set and cache line states, making it difficult forthe channel to be disturbed by other processes on the core, and they can stillwork in a cache using a random replacement policy. We also analyzed thestealthiness of WB channels from the perspective of the number of cache loadsand cache miss rates. We discuss and evaluate possible defenses. The paperfinishes by discussing various forms of side-channel attack.

Abusing Cache Line Dirty States to Leak Information in Commercial Processors