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While there is a large body of research on efficient processing of deepneural networks (DNNs), ultra-low-latency realization of these models forapplications with stringent, sub-microsecond latency requirements continues tobe an unresolved, challenging problem. Field-programmable gate array(FPGA)-based DNN accelerators are gaining traction as a serious contender toreplace graphics processing unit/central processing unit-based platformsconsidering their performance, flexibility, and energy efficiency. This paperpresents NullaNet Tiny, an across-the-stack design and optimization frameworkfor constructing resource and energy-efficient, ultra-low-latency FPGA-basedneural network accelerators. The key idea is to replace expensive operationsrequired to compute various filter/neuron functions in a DNN with Boolean logicexpressions that are mapped to the native look-up tables (LUTs) of the FPGAdevice (examples of such operations are multiply-and-accumulate and batchnormalization). At about the same level of classification accuracy, compared toXilinx's LogicNets, our design achieves 2.36$\times$ lower latency and24.42$\times$ lower LUT utilization.

NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic