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The success of Deep Artificial Neural Networks (DNNs) in many domains createda rich body of research concerned with hardware accelerators forcompute-intensive DNN operators. However, implementing such operatorsefficiently with complex hardware intrinsics such as matrix multiply is a tasknot yet automated gracefully. Solving this task often requires joint programand data layout transformations. First solutions to this problem have beenproposed, such as TVM, UNIT or ISAMIR, which work on a loop-levelrepresentation of operators and specify data layout and possible programtransformations before the embedding into the operator is performed. Thistop-down approach creates a tension between exploration range and search spacecomplexity, especially when also exploring data layout transformations such asim2col, channel packing or padding.  In this work, we propose a new approach to this problem. We created abottom-up method that allows the joint transformation of both compuation anddata layout based on the found embedding. By formulating the embedding as aconstraint satisfaction problem over the scalar dataflow, every possibleembedding solution is contained in the search space. Adding additionalconstraints and optmization targets to the solver generates the subset ofpreferable solutions.  An evaluation using the VTA hardware accelerator with the Baidu DeepBenchinference benchmark shows that our approach can automatically generate codecompetitive to reference implementations. Further, we show that dynamicallydetermining the data layout based on intrinsic and workload is beneficial forhardware utilization and performance. In cases where the referenceimplementation has low hardware utilization due to its fixed deploymentstrategy, we achieve a geomean speedup of up to x2.813, while individualoperators can improve as much as x170.

Joint Program and Layout Transformations to enable Convolutional Operators on Specialized Hardware based on Constraint Programming