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Modern SoC design relies on the ability to separately verify IP blocksrelative to their own specifications. Formal verification (FV) usingSystemVerilog Assertions (SVA) is an effective method to exhaustively verifyblocks at unit-level. Unfortunately, FV has a steep learning curve and requiresengineering effort that discourages hardware designers from using it during RTLmodule development. We propose AutoSVA, a framework to automatically generateFV testbenches that verify liveness and safety of control logic involved inmodule interactions. We demonstrate AutoSVA's effectiveness and efficiency ondeadlock-critical modules of widely-used open-source hardware projects.

AutoSVA: Democratizing Formal Verification of RTL Module Interactions