English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

In this paper, we demonstrate the design of efficient and high-performanceAI/Deep Learning accelerators with customized STT-MRAM and a reconfigurablecore. Based on model-driven detailed design space exploration, we present thedesign methodology of an innovative scratchpad-assisted on-chip STT-MRAM basedbuffer system for high-performance accelerators. Using analytically derivedexpression of memory occupancy time of AI model weights and activation maps,the volatility of STT-MRAM is adjusted with process and temperature variationaware scaling of thermal stability factor to optimize the retention time,energy, read/write latency, and area of STT-MRAM. From the analysis of modernAI workloads and accelerator implementation in 14nm technology, we verify theefficacy of our designed AI accelerator with STT-MRAM STT-AI. Compared to anSRAM-based implementation, the STT-AI accelerator achieves 75% area and 3%power savings at iso-accuracy. Furthermore, with a relaxed bit error rate andnegligible AI accuracy trade-off, the designed STT-AI Ultra acceleratorachieves 75.4%, and 3.5% savings in area and power, respectively over regularSRAM-based accelerators.

Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM