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Neural Networks (NN) have been proven to be powerful tools to analyze BigData. However, traditional CPUs cannot achieve the desired performance and/orenergy efficiency for NN applications. Therefore, numerous NN accelerators havebeen used or designed to meet these goals. These accelerators all fall intothree categories: GPGPUs, ASIC NN Accelerators and CISC NN Accelerators. ThoughCISC NN Accelerators can achieve considerable smaller memory footprint thanGPGPU thus improve energy efficiency; they still fail to provide same level ofdata reuse optimization achieved by ASIC NN Accelerators because of theinherited poor pragrammability of their CISC architecture. We argue that, forNN Accelerators, RISC is a better design choice than CISC, as is the case withgeneral purpose processors. We propose RISC-NN, a novel many-core RISC-based NNaccelerator that achieves high expressiveness and high parallelism and featuresstrong programmability and low control-hardware costs. We show that, RISC-NNcan implement all the necessary instructions of state-of-the-art CISC NNAccelerators; in the meantime, RISC-NN manages to achieve advanced optimizationsuch as multiple-level data reuse and support for Sparse NN applications whichpreviously only existed in ASIC NN Accelerators. Experiment results show that,RISC-NN achieves on average 11.88X performance efficiency compared withstate-of-the-art Nvidia TITAN Xp GPGPU for various NN applications. RISC-NNalso achieves on average 1.29X, 8.37X and 21.71X performance efficiency overCISC-based TPU in CNN, MLP and LSTM applications, respectively. Finally,RISC-NN can achieve additional 26.05% performance improvement and 33.13% energyreduction after applying pruning for Sparse NN applications.

RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure