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We demonstrate ferroelectric (FE) memory transistors on a crystalline siliconchannel with endurance exceeding $10^{10}$ cycles. The ferroelectrictransistors (FeFETs) incorporate a high-$\kappa$ interfacial layer (IL) ofthermally grown silicon nitride (SiN$_x$) and a thin 4.5 nm layer of Zr-dopedFE-HfO$_2$ on a $\sim$30 nm SOI channel. The device shows a $\sim$ 1V memorywindow in a DC sweep of just $\pm$ 2.5V, and can be programmed and erased withvoltage pulses of $V_G= \pm$ 3V at a pulse width of 250 ns. The device alsoshows very good retention behavior. These results indicate that appropriateengineering of the IL layer could substantially improve FeFET deviceperformance and reliability.

Ferroelectric HfO$_2$ Memory Transistors with High-$\kappa$ Interfacial Layer and Write Endurance Exceeding $10^{10}$ Cycles