English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Cache side-channel attacks lead to severe security threats to the settingsthat a CPU is shared across users, e.g., in the cloud. The existing attacksrely on sensing the micro-architectural state changes made by victims, and thisassumption can be invalidated by combining spatial (\eg, Intel CAT) andtemporal isolation (\eg, time protection). In this work, we advance the stateof cache side-channel attacks by showing stateless cache side-channel attacksthat cannot be defeated by both spatial and temporal isolation.  This side-channel exploits the timing difference resulted from interconnectcongestion. Specifically, to complete cache transactions, for Intel CPUs, cachelines would travel across cores via the CPU mesh interconnect. Nonetheless, themesh links are shared by all cores, and cache isolation does not segregate thetraffic. An attacker can generate interconnect traffic to contend with thevictim's on a mesh link, hoping that extra delay will be measured. With thevariant delays, the attacker can deduce the memory access pattern of a victimprogram, and infer its sensitive data. Based on this idea, we implement Volcanoand test it against the existing RSA implementations of JDK. We found the RSAprivate key used by a victim process can be partially recovered. In the end, wepropose a few directions for defense and call for the attention of the securitycommunity.

Volcano: Stateless Cache Side-channel Attack by Exploiting Mesh Interconnect