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Resistive Random-Access-Memory (ReRAM) crossbar is a promising technique fordeep neural network (DNN) accelerators, thanks to its in-memory and in-situanalog computing abilities for Vector-Matrix Multiplication-and-Accumulations(VMMs). However, it is challenging for crossbar architecture to exploit thesparsity in the DNN. It inevitably causes complex and costly control to exploitfine-grained sparsity due to the limitation of tightly-coupled crossbarstructure. As the countermeasure, we developed a novel ReRAM-based DNNaccelerator, named Sparse-Multiplication-Engine (SME), based on a hardware andsoftware co-design framework. First, we orchestrate the bit-sparse pattern toincrease the density of bit-sparsity based on existing quantization methods.Second, we propose a novel weigh mapping mechanism to slice the bits of aweight across the crossbars and splice the activation results in peripheralcircuits. This mechanism can decouple the tightly-coupled crossbar structureand cumulate the sparsity in the crossbar. Finally, a superior squeeze-outscheme empties the crossbars mapped with highly-sparse non-zeros from theprevious two steps. We design the SME architecture and discuss its use forother quantization methods and different ReRAM cell technologies. Compared withprior state-of-the-art designs, the SME shrinks the use of crossbars up to 8.7xand 2.1x using Resent-50 and MobileNet-v2, respectively, with less than 0.3%accuracy drop on ImageNet.

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network