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SU3\_Bench is a microbenchmark developed to explore performance portabilityacross multiple programming models/methodologies using a simple, butnontrivial, mathematical kernel. This kernel has been derived from the MILClattice quantum chromodynamics (LQCD) code. SU3\_Bench is bandwidth bound andgenerates regular compute and data access patterns. Therefore, on mosttraditional CPU and GPU-based systems, its performance is mainly determined bythe achievable memory bandwidth. Although SU3\_Bench is a simple kernel,experience says its subtleties require a certain amount of tweaking to achievepeak performance for a given programming model and hardware, making performanceportability challenging. In this paper, we share some of the challenges inobtaining the peak performance for SU3\_Bench on a state-of-the-art Intel Xeonmachine, due to the nuances of variable definition, the nature ofcompiler-provided default constructors, how memory is accessed at objectcreation time, and the NUMA effects on the machine. We discuss how to tacklethose challenges to improve SU3\_Bench's performance by \(2\times\) compared tothe original OpenMP implementation available at Github. This provides avaluable lesson for other similar kernels.  Expanding on the performance portability aspects, we also show early resultsobtained porting SU3\_Bench to the new Intel Programmable Integrated UnifiedMemory Architecture (PIUMA), characterized by a more balanced flops-to-byteratio. This paper shows that it is not the usual bandwidth or flops, rather thepipeline throughput, that determines SU3\_Bench's performance on PIUMA.Finally, we show how to improve performance on PIUMA and how that compares withthe performance on Xeon, which has around one order of magnitude moreflops-per-byte.

Performance Optimization of SU3_Bench on Xeon and Programmable Integrated Unified Memory Architecture