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The emergence of machine learning, image and audio processing on edge deviceshas motivated research towards power efficient custom hardware accelerators.Though FPGAs are an ideal target for energy efficient custom accelerators, thedifficulty of hardware design and the lack of vendor agnostic, standardizedhardware compilation infrastructure has hindered their adoption.  This paper introduces HIR, an MLIR-based intermediate representation (IR) todescribe hardware accelerator designs. HIR combines high level languagefeatures, such as loops and multi-dimensional tensors, with programmer definedexplicit scheduling, to provide a high-level IR suitable for DSL compilerpipelines without compromising control over the micro-architecture of theaccelerator. HIR's explicit schedules allow it to express fine-grained,synchronization-free parallelism and optimizations such as retiming andpipelining. Built as a dialect in MLIR, it draws from best IR practices learntfrom communities like those of LLVM. While offering rich optimizationopportunities and a high level abstraction, HIR enables sharing ofoptimizations, utilities and passes with software compiler infrastructure.  Our implementation shows that the code generation time of the HIR codegenerator is on average 1112x lower than that of Xilinx Vivado HLS on a rangeof kernels without a compromise on the quality of the generated hardware. Webelieve that these are significant steps forward in the design of IRs forhardware synthesis and in equipping domain-specific languages with a productiveand performing compilation path to custom hardware acceleration.

HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description