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Over the last decade the relative latency of access to shared memory bymulticore increased as wire resistance dominated latency and low wire densitylayout pushed multiport memories farther away from their ports. Varioustechniques were deployed to improve average memory access latencies, such asspeculative pre-fetching and branch-prediction, often leading to high variancein execution time which is unacceptable in real time systems. Smart DMAs can beused to directly copy data into a layer1 SRAM, but with overhead. The VLIWarchitecture, the de facto signal processing engine, suffers badly from abreakdown in lockstep execution of scalar and vector instructions. We describethe Split Latency Adaptive Pipeline (SLAP) VLIW architecture, a cacheperformance improvement technology that requires zero change to object code,while removing smart DMAs and their overhead. SLAP builds on the DecoupledAccess and Execute concept by 1) breaking lockstep execution of functionalunits, 2) enabling variable vector length for variable data level parallelism,and 3) adding a novel triangular load mechanism. We discuss the SLAParchitecture and demonstrate the performance benefits on real traces from awireless baseband system (where even the most compute intensive functionssuffer from an Amdahls law limitation due to a mixture of scalar and vectorprocessing).

SLAP: A Split Latency Adaptive VLIW pipeline architecture which enables on-the-fly variable SIMD vector-length