English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

We present systematic and efficient solutions for both observabilityenhancement and root-cause diagnosis of post-silicon System-on-Chips (SoCs)validation with diverse usage scenarios. We model specification of interactingflows in typical applications for message selection. Our method for messageselection optimizes flow specification coverage and trace buffer utilization.We define the diagnosis problem as identifying buggy traces as outliers andbug-free traces as inliers/normal behaviors, for which we use unsupervisedlearning algorithms for outlier detection. Instead of direct application ofmachine learning algorithms over trace data using the signals as raw features,we use feature engineering to transform raw features into more sophisticatedfeatures using domain specific operations. The engineered features are highlyrelevant to the diagnosis task and are generic to be applied across anyhardware designs. We present debugging and root cause analysis of subtlepost-silicon bugs in industry-scale OpenSPARC T2 SoC. We achieve a trace bufferutilization of 98.96\% with a flow specification coverage of 94.3\% (average).Our diagnosis method was able to diagnose up to 66.7\% more bugs and took up to847$\times$ less diagnosis time as compared to the manual debugging with adiagnosis precision of 0.769.

Feature Engineering for Scalable Application-Level Post-Silicon Debugging